(A Level) RISC and CISC processors, pipelining and parallel computers

Learning objectives

Compare reduced instruction set (RISC) and complex instruction set (CISC) processors on the size and format of the instruction set, the clock cycles per instruction, the use of registers and of memory, and where the complexity is placed

Explain pipelining as the overlapping of the stages of successive instructions, name the five stages of a typical RISC pipeline, and calculate the clock cycles needed with and without a pipeline

Explain why RISC processors suit pipelining and have many general-purpose registers, and why a pipeline raises the throughput without shortening the time taken by any one instruction

Describe how interrupts are handled on a CISC processor and on a pipelined RISC processor, including what happens to the instructions already in the pipeline

Describe what sets a massively parallel computer apart, and explain why communication between processors and the sequential part of a task limit the speed-up