Processor architecture and the fetch–decode–execute cycle

Learning objectives

Describe the von Neumann model of a stored-program computer, naming the arithmetic and logic unit, the control unit, the immediate access store and the registers, and explain what is meant by a stored program

State the purpose of the program counter, memory address register, memory data register, current instruction register, index register, status register and accumulator, and explain the part each plays in carrying out an instruction

Explain the purpose of the address bus, the data bus and the control bus, and describe how the width of the address bus and of the data bus limits the memory that can be addressed and the data that can be moved at once

Describe each step of the fetch–decode–execute cycle in register transfer notation, and trace the contents of the registers as a short sequence of instructions is carried out

Explain how clock speed, the number of cores, bus width and cache size each affect processor performance, and explain why raising clock speed alone gives diminishing returns

Describe how an interrupt is handled, including the test at the end of the cycle, the saving of register contents and the calling of an interrupt service routine, and (A Level) compare the SISD, SIMD, MISD and MIMD models of parallel processing

Distinguish general-purpose from special-purpose registers, state the role of the system clock, and describe how USB, HDMI and VGA ports connect peripheral devices